1. Field of the Invention
The present invention relates to a repair circuit in semiconductor memory devices, and more particularly, to a repair circuit that is applied to semiconductor memory devices for receiving a X (row) address and a Y (column) address at a time without receiving them divisionally, and semiconductor memory devices operating as a single read mode and a single write mode with no burst or a page mode without address multiplexing.
2. Background of the Related Art
In a conventional synchronous DRAM (hereinafter called ‘SDRAM’), if there occurs fail as shown in FIG. 1, the row address and the column address are first divided. Thereafter, in case of row fail, the word line may be replaced in order to repair the fail. In case of column fail, all of column select (Yi) signals may be replaced in order to repair the fail.
The row fail means that in the fail address, the row addresses are same and the column addresses are different. In this case, it would be effective to replace the entire word lines with a corresponding the row address. Likewise, the column fail means that in the fail address, the column addresses are same and the row addresses are different. At this time, it would be effective to replace the column address with a corresponding column select (Yi) signal.
However, random bit fail not row and column fail means that only 1 (one) bit is fail. Likewise in the above, the only 1 bit having fail is not replaced but all the row and column addresses of fail addresses are replaced. For example, if X=00 is inputted, a repaired word line is enabled regardless of the column address. This is not the type in which only one bit is replaced.
Referring now to FIG. 1, the conventional repair circuit will be described in detailed.
As shown in FIG. 1, the repair circuit includes an row repair block 100, a column repair block 200 and a cell block 300.
If fail 0 being random bit fail occurs, addresses corresponding to the row address are replaced, whereby the entire word lines are changed from a normal word line to a repair word line.
If fail 1 being random bit fail occurs, only the column address is replaced, whereby the entire column addresses are changed from the normal column address to the repair column address in the cell block 300.
FIG. 2 is a detailed circuit diagram of the row repair block 100 shown in FIG. 1.
The row repair block 100 has fuses X fuse as many as the number of the repair word line.
In FIG. 2, the cell block 300 includes N number of blocks each having repair word line. However, this is not true in all the memory semiconductors. The blocks are related to the repair efficiency. Therefore, a small number of the blocks may be added and a large number of the blocks may be added. A cell matrix is divided into N numbers and may be inserted into every block. Otherwise, the repair word line for repairing fail may be located at one position. Though there are many cases, but there is no difference in the method of repairing fail except that only its arrangement is different. It is shown in FIG. 2 that the cell block 300 is largely divided into N numbers, there are N numbers of the repair word line and N numbers of the fuses X fuse within the row repair block corresponding to the repair word line. Further, there are N numbers of repair word line drivers 10 for driving the repair word line. Also, the repair circuit of FIG. 2 includes a fuse summation block 110 for summating an output signal rwl_enb_n of each of the fuses X fuse.
Referring now to FIG. 3, the operation of the fuse summation block 110 will be described. The block 110 performs a NAND combination for the output signals rwl_enb-0, rwl_enb_1, . . . , rwl_enb_n of each of the fuses to produce a fuse summation signal Fuse_sumb. The output signal rwl_enb_n is a signal to keep Low level when the failed row address is inputted since the row address with fail is set in the fuse and to shift from Low level to High level when a normal address (not the failed row address) is inputted. Therefore, the normal address shifts from Low level to High level same to the fuse summation signal Fuse_sumb. The failed row address keeps Low level. The fuse summation block 110 has an output signal of Low level when at least one of the input signals keep Low level, which may be said a simple AND combination of the input signal. This is because the input signal is enabled to be Low level. If it is a circuit the input signal of which is enabled to be High level, it is required that fuse summation block 110 be OR-combined. This is the circuit the input signal of which is enabled to be Low level. The fuse summation signal Fuse_sumb is used as an enable signal in the normal word line driver 20 and also used as a signal to drive the repair word line along with the output signal rwl_enb_n.
If the output signal rwl_enb_n keeps Low level and the fuse summation signal Fuse_sumb keeps Low level, the repair word line is enabled. Only one of the output signals rwl_enb_n from 0 to n becomes Low level. The repair word line is driven in the block that became Low level.
In the normal word line driver 20, the output signal rwl_enb_n that became Low level is used as a disable signal. In other words, if the output signal rwl_enb_n becomes Low level, the path along which the normal word line operates is disabled. Also, if the output signal rwl_end_n becomes High level, the normal word line operates. At this time, all the normal word lines do not operate but the normal word line corresponding to the row address operates.
By reference to FIG. 4, the column repair block 200 will be described.
The block 200 corresponds to a repair circuit for the column address.
This block includes a column fuse box 30, a repair column select unit 40 and a normal column select unit 50 as main components. The column fuse box 30 will be first explained. The column fuse enable signal Yfuse_enable is a signal generated when the word line is enabled by the row address.
If the fuse enable signal Yfuse_enable is inputted, the column fuse box 30 is ready to operate. At this time, if the column address is inputted, the box 30 discriminates whether the address is a fail address or a normal address to output the output signal Ryi_enb. If the column address is the fail address, the output signal Ryi_enb becomes Low level to enable the repair column select unit 40, which drives the column repair driver 60. Due to this, a repair column select signal Repair Ys is enabled. Further, the signal Ryi_enb makes the normal column select unit 50 disabled, so that the normal column select signal Normal Ys is not outputted. On the contrary, when the output signal Ryi_enb keeps High level, the normal column select unit 50 receives the column address to drive the normal column driver 70 corresponding thereto, thereby enabling the normal column select signal Normal Ys. At this time, the normal column driver 70 and the normal column select unit 50 exist as many as the number of the column address.
As in the above, most of the memory semiconductors are constructed to divide the row and column addresses in order to repair fail. Of course, it would be reasonable that SDRAM is constructed as in the memory semiconductors since the row and column addresses are inputted from the outside separately. In case of SRAM, the row and column addresses are not inputted thereto dividedly but are internally dividedly used. Thus, if fail is repaired for surrounding addresses and row addresses as well as failed addresses, there is a possibility that column addresses corresponding to a block in which the memory cells are divided as well as the failed column addresses are all changed. This may cause a problem that addresses with no fail are replaced. In this case, though the failed Y addresses in the replaced row address could be repaired, fail may occur in other addresses.